1. Field of Invention
The present invention relates generally to design verification systems for integrated circuits (ICs) and more particularly to the use of hardware-based functional verification systems for verifying power shutoff behavior of IC designs.
2. Description of Related Art
The development of EDA (electronic design automation) tools has included a number of hardware-based functional verification systems including logic emulation systems and simulation accelerators. For simplicity these tools will be referred to collectively as emulation systems in the subsequent discussion.
Emulation systems can be used to verify the functionalities of electronic circuit designs prior to fabrication as chips or as electronic systems. Typical emulation systems utilize either interconnected programmable logic chips or interconnected processor chips. Exemplary hardware logic emulation systems with programmable logic devices are described, for example, in U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191, and exemplary hardware logic emulation systems with processor chips are described, for example, in U.S. Pat. Nos. 5,551,013, 6,035,117 and 6,051,030. Each of these patents is incorporated herein by reference in its entirety.
The DUT (Design Under Test) is usually provided in the form of either an RTL (Register Transfer Level) description or a gate level netlist. The gate level netlist may have been derived from RTL sources, including from a hardware description language (HDL), such as Verilog or VHDL (VHSIC (Very High Speed Integrated Circuit) HDL), using a synthesis method. Both RTL and gate level netlists are descriptions of the circuit's components and electrical interconnections between the components, where these components include all circuit elements, such as combinatory logic (e.g., gates) and sequential logic (e.g., flip-flops and latches), necessary for implementing a logic circuit.
Emulation systems have certain advantages over software simulation tools, which are conventionally used to create models of a user's design that can be simulated at a computer workstation, typically in a serial operations a single or a small number of CPUs (Central Processing Units). In contrast, hardware-based systems have dedicated hardware that will perform the designed functions in parallel. This massive parallelism enables a hardware-based system to operate at a speed that is orders of magnitude faster than a software simulator. Because emulators can operate so much faster than simulators, they can perform functional verification much faster. For example, an emulator can execute thousands of clock cycles of a DUT in a few milliseconds. Thus, in the same amount of time an emulator executes millions of clock cycles, a software simulator might only have simulated the execution of a few or even just a fraction of a clock cycle. In fact, emulators can operate at speed fast enough to allow the intended application software to run on the prototype system, which is something the software simulator can never accomplish.
Another advantage of hardware-based systems over simulation is their ability to operate “in circuit”. Operating “in circuit” refers to an emulator's ability to operate in the actual hardware that the DUT being emulated will eventually be installed into once it has been fabricated. This actual hardware is sometimes referred to as the “target system”. For example, the designer of a microprocessor might emulate the microprocessor design. Using a cable connecting the emulator to the motherboard of a personal computer, the emulator can be used in lieu of the actual microprocessor. The ability to operate in circuit provides many advantages. One of them is that the designer can see how their design functions in the actual system in which the DUT will eventually be installed. Another advantage is that in circuit emulation allows software development to take place before the IC chip is fabricated. Thus, the emulator can emulate the IC in the target system while the design team writes firmware and tests other application software.
Low-power designs for ICs (e.g., for applications in wireless and portable electronics) have led to additional challenges for design verification including minimizing leakage power dissipation, designing efficient packaging and cooling systems for high-power integrated circuits, and verifying functionalities of low-power or no power situations early in the design. These power management issues have become even more critical in view of the continuous shrinking of device dimensions with the next generation of semiconductor processing technology.
However, conventional emulation systems have not responded to these challenges. One reason is that existing power optimization and implementation techniques are typically applied at the physical implementation phase of the design process (e.g., after circuit synthesis). These power management design techniques may significantly change the design intent, yet none of the intended behavior can be captured in the RTL of the design. This deficiency creates a gap in the RTL to Graphic Data System II (GDSII) implementation and verification flow where the original RTL can no longer be relied upon as a correct representation of the design, and thus cannot be used to verify the final netlist implementation containing power management implementations.
One approach to power management for low power designs has been the development of a Common Power Format (CPF), which enables designers to specify design intents such as power management information in a single file that can be shared by different design tools in the entire design flow, all the way from RTL to GDSII implementation. Consistent power management analysis can be maintained across relevant design stages including verification, synthesis, testing, physical implementation and signoff analysis. (Chi-Ping Hsu, “Pushing Power Forward with a Common Power Format—The Process of Getting it Right,” EETimes, 5 Nov. 2006.) However, conventional emulation systems have not incorporated these aspects so as to enable hardware-based verification of critical power management functions such as power shutoff, cell isolation and state retention in a low power design.
Thus there is a need for improved emulation systems for verifying power shutoff behavior of IC designs.